One conventional wafer level CSP style, (commonly referred to as “flip chip” packaging), generally contemplates forming solder bumps (or other suitable contacts) directly on I/O pads (bump pads) formed on an IC die. FIG. 1 is a side view of a conventional flip chip type device. The flip chip 100 includes a die 102 that typically has a plurality of IC device structures in the active region 112. These IC device structures may include, for example, transistors and interconnect layers. The die 102 has a top surface (active surface or frontside) 104 that includes bump pads (not shown). Solder bumps 106 are formed on the bump pads of the top surface 104, which is opposite a bottom surface (backside) 108 of the die 102. In between the top surface 104 and bottom surface 108 are side surfaces 110. A plurality of flip chip dice 102 are typically formed on the surface of a wafer (not shown). After the dice 102 are formed on the wafer, each die 102 is separated from the wafer in a dicing or singulation operation.
Flip chip devices may be mounted in larger package structures or directly on a printed circuit board or other substrate. One problem that has been observed in some flip chip applications is the photo-generation of electrons within the die when a surface of the die is exposed to light. That is, the IC devices may have functional problems due to photogenerated carriers when a surface (e.g., 108, 104, 110) of the die (e.g. 102) is exposed to light, or the IC devices may be subject to an undesirable electrostatic shock during handling of the device subsequent to the dicing operation.
U.S. Pat. Nos. 6,352,881 and 6,023,094, disclose methods of addressing the problem by applying an opaque protective layer to the top surface and/or bottom surface of the flip chip die during wafer processing. That is, the backside and/or frontside of the wafer is coated with a protective film or fill material in order to block any light that may be incident on those respective surfaces. These patents contemplate applying the light blocking materials at the wafer level, which has significant costs advantages when compared to individually coating the dice after the wafer has been singulated.
Although the described wafer level flip chip packaging approaches work quite well, there are continuing efforts to provide further improved wafer level packaging processes and structures that facilitate the use of flip chip packages in even more application.